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This short tutorial aims at teaching how to run CADENCE CAD tools on the Sun workstation. The setup is just for the environment of the Department of Electrical Engineering, Arizona State University. Outside users need to modify some setup files for their own environment. Graphic User Interfaces may vary dependent upon the Cadence Toolset Version being used.
- Setting up Unix Environment
- Schematic Entry with Composer
- Generating Symbol View
- Simulation in Spectre(S)
- Layout Editor
- Design Verification: DRC and Extraction
- LVS and Post Extraction Simulation
Now, AMI 0.6µm Standard Cell Library is available: click here and the NCSU Cadence Design Kit Version 1.4 can be downloaded here.
Find a tip here for creating Corners and running simulation.
EEE classes using the Cadence Toolset are:
- EEE 425 : Digital Systems and Circuits
- Course Description : Digital logic gate analysis and design. Propagation delay times, fan out, power dissipation, noise margins. Design of MOS and bipolar logic families, including NMOS, CMOS, standard and advanced TTL, ECL, and BiCMOS. Inverter, combinational and sequential logic circuit design, MOS memories, VLSI circuits. Computer simulations using PSPICE.
- EEE 433 : Analog Integrated Circuits
- Course Description : Analysis, design, and applications of modern analog circuits using integrated bipolar and field effect transistor technologies.
- Products used :
- Composer for schematic entry and as our primary design environment
- Symbol editor for using a hierarchical design and creating test benches
- The spectre simulator in the Analog Design Environment
- DC, Transient, and AC analyses for basic design simulations
- DC and AC sweeps and the Parametric Analysis tool for rapid design variation
- Periodic Steady State Analysis for Fourier/Distortion analysis
- The Calculator for waveform arithmetic operations: (e.g. power and THD)
- Virtuoso for layout entry, schematic realization
- DRC
- LVS
- Extraction and back annotation
- Simulations, same as performed on schematic design
- EEE 517 : Hardware Design Languages
- Course Description : Introduces hardware design languages. Modeling concepts for specification, simulation, and synthesis.
- Products used :
- Virtuoso Front to Back Design Environment 5.10.41.500.0.7
- Schemetic Design : Virtuoso Schemetic Editor 5.10.41.500.0.7
- Layout design : Virtuoso Layout Editor 5.10.41.500.0.7
- Analysis : Virtuoso Analog Design Environment
- Simulator : Spectre/SpectreS/HSPICE/Verilog/SpectreVerilog
- Verification in the Layout : DRC, LVS and Extractor
- Specific tool-kits used : For EEE527 : Obtained from NCSU (TSMC 0.60um, TSMC 0.40um, TSMC 0.30um, TSMC 0.18um )
- process used yet to be decided
- EEE 523 : Advanced Analog Integrated Circuits
- Course Description : Analysis and design of analog integrated circuits: analog circuit blocks, reference circuits, operational-amplifier circuits, feedback, and nonlinear circuits.
- EEE 524 : Communications Transceiver Circuits Design
- Course Description : Analysis and design of Very Large Scale Integrated (VLSI) circuits. Physics of small devices, fabrication, regular structures, and system timing. Open only to graduate students.
- Product used :
- Cadence Toolsuite : v5.1.0
- Design Entry : Virtuoso Schematic Editor
- Layout : Virtuoso Layout XL
- Simulation : Analog Design Environment, choice of simulator: Spectre/SpectreS/HSPICE/Verilog/SpectreVerilog
- DRC+LVS : Diva + Assura
- EEE 525 : VLSI Design
- Course Description : Analysis and design of Very Large Scale Integrated (VLSI) circuits. Physics of small devices, fabrication, regular structures, and system timing.
- Product used :
- Cadence Toolsuite : v5.1.0
- Design Entry : Virtuoso Schematic Editor
- Layout : Virtuoso Layout XL
- Simulation : Analog Design Environment, choice of simulator: Spectre/SpectreS/HSPICE/Verilog/SpectreVerilog
- DRC+LVS : Diva + Assura
- Specific tool-kits used : Obtained from NCSU (HIP 1.6um, TSMC 0.40um, TSMC 0.30um, TSMC 0.18um )
- 0.25µm use for the class.
- EEE 527 : Analog to Digital Converters
- Course Description : Detailed introduction to the design of Nyquist rate, CMOS analog to digital converters.
- Products used :
- Virtuoso Front to Back Design Environment 5.10.41.500.0.7
- Schemetic Design : Virtuoso Schemetic Editor 5.10.41.500.0.7
- Layout design : Virtuoso Layout Editor 5.10.41.500.0.7
- Analysis : Virtuoso Analog Design Environment
- Simulator : Spectre/SpectreS/HSPICE/Verilog/SpectreVerilog
- Verification in the Layout : DRC, LVS and Extractor
- Specific tool-kits used : Obtained from NCSU (TSMC 0.60um, TSMC 0.40um, TSMC 0.30um, TSMC 0.18um )
- 0.45µm use for the class.
Research Projects using the Cadence Toolset are:
- Connection One
- Mission Statement : Connection One is a National Science Foundation Industry/University Cooperative Research Center established by the Arizona State University Ira A. Fulton School of Engineering. The primary focus of Connection One is on communication circuits and systems to enable higher integration and smaller communication devices to facilitate system-on-a-chip (SOC).
- Products used :
- Cadence Toolsuite : v5.1.0
- Design Entry : Virtuoso Schematic Editor
- Layout : Virtuoso Layout XL
- Simulation : Analog Design Environment, choice of simulator: Spectre/SpectreS/HSPICE/Verilog/SpectreVerilog/Ultrasim
- DRC+LVS : Diva + Assura
- WINTech
- The goal of WINTech is to improve the current standard of living through the design and advancement of small, highly integrated electrical and electro-mechanical systems.
- Products used:
- Cadence Toolsuite : v5.1.0
- Design Entry : Virtuoso Schematic Editor
- Layout : Virtuoso Layout XL
- Simulation : Analog Design Environment, choice of simulator: Spectre/SpectreS/HSPICE/Verilog/SpectreVerilog/Ultrasim
- DRC+LVS : Diva + Assura
- Computing Systems Research Lab
Cadence Links:
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2655 Seely Avenue, San Jose, CA 95134
Page created and maintained by: James Laux
Contact Information:
Connection One / WINTech Research Centers
Ira A. Fulton School of Engineering
Arizona State University
Goldwater Bldg. Room 374
Tempe, Arizona 85287
Phone: 480.727.8581
Last Updated: June 20. 2008 8:22am